1. Field of the Invention
The present invention relates to a computer provided with a pipeline processing function of instructions.
2. Description of the Prior Art
FIG. 2 is a block diagram of a microprocessor operating as a conventional computer provided with a pipeline processing function of instructions and a target predicting function of branch instructions. In the drawing, 1 denotes an instruction prefetch queue as an instruction prefetch device, 2 denotes an instruction decoding unit as an instruction analyzer, 3 denotes an instruction execution unit as an instruction running device, and 4 denotes a branch target buffer as a target predictor for predicting targets of branch instructions and others.
An operation of the microprocessor will be described next.
An instruction to be executed next is decoded by the instruction decoding unit 2 while instructions are executed by the instruction execution unit 3, and when instructions have been executed by the instruction execution unit 3, the next instruction already decoded by the instruction decoding unit 2 is executed quickly. In this case, the instruction prefetch queue 1 prefetches instructions from a storage (hereinafter called main storage) for storing a plurality of instructions in a plurality of areas ordered by first, second, third, fourth . . . area recognition symbols (hereinafter called addresses) according to a fixed regulation during the period of time when the main storage is not accessed, and the time required for fetching instructions is shortened by the instruction decoding unit 2 fetching the instruction data to be coded next from the instruction prefetch queue 1.
Generally in case a flow of instructions is disordered, or when a branch instruction is executed, for example, the instruction decoding unit 2 and the instruction prefetch queue 1 are canceled, and the instruction prefetch queue 1 carries out a queuing newly from the target address. That is, the instruction to be run for the first time after execution of a jump instruction must be fetched directly from the main storage, the instruction execution unit 3 must suspend execution of instructions until the instruction to be executed next is fetched and decoded, however, what is called branch target buffer 4 is used to improve the problem. The buffer is that in which an address of the branch instruction, a target address thereof and a flag indicating whether or not the branch instruction is branched actually when executed previously are stored in a set, and is a target address prediction mechanism for predicting the target address before executing the branch instruction. It has been found that a flow of program can be predicted fairly at a high probability according to how it is predicted.
Next, the operation will be described.
When an instruction data is fetched to the instruction decoding unit 2 from the instruction prefetch queue 1, the instruction decoding is commenced and the branch target buffer 4 is referred at address of the instruction. When a branching is predicted by the branch target buffer 4, the instruction prefetch queue 1 is cleared, a queuing is carried out from the predicted target address, and the fetched instruction code is delivered to the instruction decoding unit 2. Then, if the prediction is hit, the pipeline processing will not be disturbed influentially as the instruction to be executed next by the instruction execution unit 2 is already decoded by the instruction decoding unit 2.
Thus, a disturbance of the pipeline processing after execution of the branch instruction is suppressed by providing the branch target buffer 4 additionally, thereby raising an effective computing speed of the computer.
Then, an example of the pipeline processing microprocessor provided with a normal instruction prefetch queue is given in "Processor Architecture", iAPX 286 "Hardware Reference Manual" issued by INTEL in 1983.
Further, a configuration example of the branch target buffer is shown in "Branch Prediction Strategies and Branch Target Buffer Design", "COMPUTER" Volume 17 Number 1, issued by IEEE in Jan. 1984.
In the conventional computer described as above, while a disturbance of the pipeline processing is suppressed by prediction of a target address through the branch target buffer 4 provided therefor, in case a target prediction of the branch instruction is missed to no branching, an execution must be suspended until the instruction in the address indicated by a new program counter is fetched from the main storage, and thus the pipeline processing is disturbed to deteriorate an effective processing rate.